VLSI PROJECTS |
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CODE |
PROJECT TITLE |
IEEE YEAR |
VIE01 |
A Novel Carry-Look ahead Approach to an Unified BCD and Binary Adder/ Subtractor | IEEE-2008 |
VIE02 |
Speculative Carry Generation with Prefix Adder Using VHDL / Verilog | IEEE-2008 |
VIE03 |
Improving Error Tolerance For Multithreaded Register Files | IEEE-2008 |
VIE04 |
Higher Radix and Redundancy Factor for Floating Point Sort Division using VHDL/ Verilog | IEEE-2008 |
VIE05 |
Area-Efficient Arithmetic Expression Evaluation using Deeply Pipelined Floating Point Cores using VHDL | IEEE-2008 |
VIE06 |
Reconfigurable Architecture for Network Flow Analysis | IEEE-2008 |
VIE07 |
The Reconfigurable Instruction Cell Array | IEEE-2008 |
VIE08 |
System Architecture and Implementation of MIMO Sphere Decoders on FPGA | IEEE-2008 |
VIE09 |
Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays | IEEE-2008 |
VIE10 |
Register for Phase Difference Based Logic | IEEE-2007 |
VIE11 |
Designing Efficient Online Testable Reversible Adder with New Reversible Gate | IEEE-2007 |
VIE12 |
High Speed Recursion Architecture for Map- Based Turbo Decoders | IEEE-2007 |
VIE13 |
Concurrent Error Detection in Reed Solomon Encoders and Decoders | IEEE-2007 |
VIE14 |
LFSR-Reseeding Scheme Achieving Low-Power Dissipation during Test | IEEE-2007 |
VIE15 |
FPGA Implementation of Low Power Parallel Multiplier | IEEE-2007 |
VIE16 |
Low Power Multiplier with Superious Power Suppression Technique | IEEE-2007 |
VIE17 |
Abstraction and Refinement Techniques in Automated Design Debugging | IEEE-2007 |
VIE18 |
Concurrent Error Detection in Reed Solomon Encoders and Decoders | IEEE-2007 |
VIE19 |
Implementation of AES on A Dynamically Reconfigurable Architecture | IEEE-2007 |
VIE20 |
Designing Efficient Online Testable Reversible Adder with New Reversible Gate | IEEE-2007 |
VIE21 |
FPGA Implementation of Low Power Parallel Multiplier | IEEE-2007 |
VIE22 |
Compact Hardware Design of Whirlpool Hashing Core | IEEE-2007 |
VIE23 |
A Combined Gate Replacement and Input Vector Control Approach for Leakage Current Reduction | IEEE-2006 |
VIE24 |
A High Efficiency fully Digital Synchrouns Buck Converter Power Delivery System Based on Finite State Machine | IEEE-2006 |
VIE25 |
X-Masking During Logic BIST and Its Impact on Defect Coverage | IEEE-2006 |
VIE26 |
New techniques for untreatable fault identification in sequential circuits | IEEE-2006 |
VIE27 |
New and Improved BIST Diagnosis Method from combinatorial group testing theory | IEEE-2006 |
VIE28 |
Energy Management for battery powered Reconfigurable computing platforms | IEEE-2006 |
VIE29 |
Design specific path delay testing in look up table based FPGA | IEEE-2006 |
VIE30 |
Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison | IEEE-2006 |
VIE31 |
Improving Linear Test Data Compression | IEEE-2006 |
VIE32 |
Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction | IEEE-2006 |
VIE33 |
Extraction Error Modeling and Automated Model Debugging in High-Performance Custom Designs | IEEE-2006 |
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